integrated circuit systems, inc. general description features ICS9160-03 block diagram frequency generator and integrated buffer for powerpc ? 9160-03 revc 06/19/97p the ICS9160-03 generates all clocks required for high speed risc microprocessor systems based on the powerpc 603 and 604. five different frequency multiplying factors are selectable and offer smooth frequency transitions. bclk signals are synchronous to pclk and operate at pclk/2 for optimum synchronous pci bus performance. the multiplying and ratio factors can be customed for specific applications. both individual and group glitch-free stop and start ofthe clock signals are provided, as well as a power-down mode to mize power consumption. the individual stop and start is provided through a serial interface control. a global output enable pin simplifies production board testing, and a test mode is available to aid in system design and diagnostics. ? generates four processor and seven synchronous bus clocks plus graphic, floppy, keyboard and reference clocks ? selectable 33.3/50/60/66.6/80 mhz pclks ? 150ps maximum powerpc pll in-band jitter ? all synchronous clocks skew matched to 250ps ? individual or group stop-clock control ? power-down modes minimize standby current ? custom configurations available ? 3.0v - 5.5 supply range ? 32-pin soic package pin configuration 28-pin soic product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. preliminary product preview
2 ICS9160-03 preliminary product preview pin descriptions * frequencies assuming an input or crystal of 14.318 mhz. ** device provides 18pf load capacitance for crystal. pin number pin name type description 2x1in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 10-30 mhz xtal.** 3 x2 out xtal output which includes xtal load capacitance.** 1 4 vddx gndx pwr xtal oscillator circuit and refclk output power supplies. 5, 6, 7 fs(0:2) in frequency selection address pins. these inputs have pull-ups. 8, 9, 11, 12 pclk(0:3) out processor clock outputs which are a multiple of the input reference frequency as shown in the table below. 10, 17 13 vddp gndp pwr pclk power supplies. vddp powers the internal pclk pll and the pclk(0:3) outputs. 14 sdata in serial stop clock data is clocked in on the falling edge of bclk. a total of 15 bits must be clocked in using the following protocol. sdata is sampled on the falling edge of bclk, so the data generator should change data on the rising edge of bclk to ensure proper communication. sdata must be low for one bclk period as a start bit. the next 15 rising edges of bclk will clock data in serially. the 16th clock enables the serial data to take effect. outputs associated with serial data bits that are a one will continue without interruption. clocks associated with serial data bits that are a zero will be stopped in the low state glitch-free, that is, no short clocks with the exception of refclk and keybd which do not stop. this input has an internal pull-up device. 15, 16 stop(0:1) in stop clock control pins used for glitch-free start and stop of the clock outputs as described in the table on the next page. these inputs have internal pull-up devices. 18 refclk out buffered copy of the crystal reference frequency. 19, 21, 22, 24, 25, 27, 28 bclk(0:6) out bus clock outputs having selectable frequency based on the fs(0:2) inputs (see table on next page). 20 23 gndb vddb pwr bclk power supplies. vssb and vddb power bclk(0:6). 26 29 gndf vddf pwr fixed clock power supplies. vssf and vddf power graphic, floppy and keybd outputs plus the fixed clock pll. 30 floppy out the floppy clock output operates at 24 mhz..* 31 keybd out the keyboard clock output operates at 12 mhz.* 32 graphic out the graphics system clock output operates at 40 mhz.*
3 ICS9160-03 preliminary product preview functionality fs2 fs1 fs0 x1, refclk (mhz) pclk (0:3) (mhkz) bclk (0:6) (mhz) graphic (mhz) floppy (mhz) keybd (mhz) 0* 0* 0* tristate tristate tristate tristate off tristate 0* 0* 1* h/l* off off h/l* h/l* h/l* 0 1 0 14.318 33.3 16.6 40.0 24.0 12.0 0 1 1 14.318 50.0 25.0 40.0 24.0 12.0 1 0 0 14.318 60.0 30.0 40.0 24.0 12.0 1 0 1 14.318 66.6 33.3 40.0 24.0 12.0 1 1 0 14.318 80.0 40.0 40.0 24.0 12.0 1 1 1 tclk** tclk/2 tclk/4 tclk/3 tclk/5 tclk/10 * the oscillator and all plls are stopped to minimize power consumption in modes 000 and 001. all outputs maintain their last stable value in mode 001. control signals stop0 and stop1 can be used to ensure glitc h-free start and stop when entering mode 001, provided mode 001 is entered after the clocks have stopped and exited 10ms (maximum pll lock time) prior to starting clocks. ** x1 is externally driven with tclk in mode 111. group clock control stop1 + stop0 + sdata * pclk (0:1) pclk (2:3) bclk (0;6) graphic, floppy keybd, refclk 0 0 1 low low low low running 0 1 1 low low running running running 1 0 1 low running running running running 1 1 1 running running running running running outputs stop and start glitch-free within on-clock period. outputs will not change state if the plls are off. * each output can be stopped and started glitch-free as described in the sdata pin description above. +sdata control and stop(0:1) control are logically ored for each individual clock.
4 ICS9160-03 preliminary product preview note 1: parameter is guaranteed by design and characterization. not 100% tested in production. absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd C0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0 to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . C65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. v dd = 3.0 C 3.7 v, t a = 0 C 70 c unless otherwise stated dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.2vdd v input high voltage v ih 0.7vdd - - v input low current i il v in =0v - 10.5 28.0 ma input high current i ih v in =v dd -5.0 - 5.0 ma output low current i ol 1 v ol =0.8v; for pclks & bclks 30.0 47.0 - ma output high current i oh 1 v ol =2.0v; for pclks & bclks - -66.0 -42.0 ma output low current i ol 1 v ol =0.8v; for fixed clks 25.0 38.0 - ma output high current i oh 1 v ol =2.0v; for fixed clks - -47.0 -30.0 ma output low voltage v ol i ol =15ma; for pclks & bclks -0.30.4v output high voltage v oh 1 i oh =-30ma; for pclks & bclks 2.4 2.8 - v output low voltage v ol 1 i ol =12.5ma; for fixed clks - 0.3 0.4 v output high voltage v oh 1 i oh =-20ma; for fixed clks 2.4 2.8 - v supply current i cc @66.66 mhz; all outputs unloaded -60130ma
5 ICS9160-03 preliminary product preview note 1: parameter is guaranteed by design and characterization. not 100% tested in production. note 2: jitter spectrum meets powerpc pll natural frequency in-band requirements of less than 150ps. electrical characteristics at 3.3v v dd = 3.0 C 3.7 v ac characteristics parameter symbol test conditions min typ max units rise time t r 1 20pf load, 0.8 to 2.0v - 1.5 3 ns fall time t f 1 20pf load, 2.0 to 0.8v - 0.9 2 ns rise time t r 1 20pf load, 20% to 80% - 2 4.5 ns fall time t f 1 20pf load, 80% to 20% - 1.8 4.25 ns duty cycle d t 1 20pf load 40 50 60 % jitter, one sigma t j1s 1 pclk & bclk clocks; load=20pf, fout>25 mhz -50150ps jitter, absolute t jab 1 pclk & bclk clocks; load=20pf, fout>25 mhz -250 - 250 ps jitter, one sigma t j1s 1 fixed clk and bclk < 25 mhz and fixed clk; load=20pf -3.0 1 3.0 % jitter, absolute t jab 1 fixed clk and bclk < 25 mhz; load=20pf -5.0 2 5.0 % input frequency f i 1 - 14.318 - mhz clock skew t sk 1 pclk to pclk; load=20pf; @1.4v -250 50 250 ps clock skew t sk 1 bclk0 to other bclk; load=20pf; @1.4v -500 90 500 ps clock skew t sk 1 pclk to bclk; load=20pf; @1.4v 1 2.6 5 ns
6 ICS9160-03 preliminary product preview the data is latched into the internal shift register on the falling edge of the bclk signal with the bclk as a reference (see waveform above). the sdata input pattern will change at the bclk rising edges and must be stable for loading into the shift register at the bclk falling edges. programming bit addresses the following table lists the function of each of the 15 input programming bits for the device. ICS9160-03 sdata serial stop clock input pin bit pattern bit# output pin stop clock function (clocks stops if bit=low) 0 start bit (one "zero" bit needed to start shift register sequence.) 132graphic 2n/a 330floppy 4 28 bclk6 5 27 bclk5 6 21 bclk4 7 22 bclk3 8 24 bclk2 9 25 bclk1 10 19 bclk0 11 n/a 12 12 pclk3 13 11 pclk2 14 9 pclk1 15 8 pclk0
7 ICS9160-03 preliminary product preview 32-pin soic package ordering information ics9160m-03 pattern number (2 or 3 digit number for parts with rom code patterns) package type m=soic device t ype (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx m - ppp lead count 32l dimensonl .804 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.
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